diff options
author | Dave Airlie <airlied@redhat.com> | 2016-07-08 13:42:41 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2016-07-08 13:42:41 +1000 |
commit | 6f6e68b383314ab10189f983fead55437c149f32 (patch) | |
tree | a9254f00bb2053aa567981c8979c9713d648346c /drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | |
parent | b33e07731c13f2a9ec5c345b8542cae5adf74235 (diff) | |
parent | b1814a1def0564a2a1d3be7fa5bf7243ff899a28 (diff) |
Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
This is the main 4.8 pull for radeon and amdgpu. Sorry for the delay,
I meant to send this out last week, but I was moving house. Lots of
changes here:
- ATPX improvements for better dGPU power control on PX systems
- New power features for CZ/BR/ST
- Pipelined BO moves and evictions in TTM
- GPU scheduler improvements
- GPU reset improvements
- Overclocking on dGPUs with amdgpu
- Lots of code cleanup
- Bug fixes
* 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (191 commits)
drm/amd/powerplay: don't add invalid voltage.
drm/amdgpu: add read/write function for GC CAC programming
drm/amd/powerplay: add definitions related to di/dt feature for fiji and polaris.
drm/amd/powerplay: add shared definitions for di/dt feature.
drm/amdgpu: remove gfx8 registers that vary between asics
drm/amd/powerplay: add mvdd dpm support.
drm/amdgpu: get number of shade engine by cgs interface.
drm/amdgpu: remove more of the ring backup code
drm/amd/powerplay: Unify family defines
drm/amdgpu: clean up ring_backup code, no need more
drm/amdgpu: ib test first after gpu reset
drm/amdgpu: recovery hw jobs when gpu reset V3
drm/amdgpu: abstract amdgpu_vm_is_gpu_reset
drm/amdgpu: add a bool to specify if needing vm flush V2
drm/amdgpu: add amd_sched_job_recovery
drm/amdgpu: force completion for gpu reset
drm/amdgpu: block ttm first before parking scheduler
drm/amd: add amd_sched_hw_job_reset
drm/amd: add parent for sched fence
drm/amdgpu: remove evict vram
...
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 74 |
1 files changed, 67 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c index db23a4068baf..44658451a8d2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c @@ -73,17 +73,18 @@ void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) if (!tmp) { phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CAC); fiji_hwmgr->fast_watermark_threshold = 100; - tmp = 1; - fiji_hwmgr->enable_dte_feature = tmp ? false : true; - fiji_hwmgr->enable_tdc_limit_feature = tmp ? true : false; - fiji_hwmgr->enable_pkg_pwr_tracking_feature = tmp ? true : false; + if (hwmgr->powercontainment_enabled) { + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment); + tmp = 1; + fiji_hwmgr->enable_dte_feature = tmp ? false : true; + fiji_hwmgr->enable_tdc_limit_feature = tmp ? true : false; + fiji_hwmgr->enable_pkg_pwr_tracking_feature = tmp ? true : false; + } } } @@ -459,6 +460,23 @@ int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr) return result; } +int fiji_disable_smc_cac(struct pp_hwmgr *hwmgr) +{ + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC) && data->cac_enabled) { + int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_DisableCac)); + PP_ASSERT_WITH_CODE((smc_result == 0), + "Failed to disable CAC in SMC.", result = -1); + + data->cac_enabled = false; + } + return result; +} + int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); @@ -528,6 +546,48 @@ int fiji_enable_power_containment(struct pp_hwmgr *hwmgr) return result; } +int fiji_disable_power_containment(struct pp_hwmgr *hwmgr) +{ + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment) && + data->power_containment_features) { + int smc_result; + + if (data->power_containment_features & + POWERCONTAINMENT_FEATURE_TDCLimit) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_TDCLimitDisable)); + PP_ASSERT_WITH_CODE((smc_result == 0), + "Failed to disable TDCLimit in SMC.", + result = smc_result); + } + + if (data->power_containment_features & + POWERCONTAINMENT_FEATURE_DTE) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_DisableDTE)); + PP_ASSERT_WITH_CODE((smc_result == 0), + "Failed to disable DTE in SMC.", + result = smc_result); + } + + if (data->power_containment_features & + POWERCONTAINMENT_FEATURE_PkgPwrLimit) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable)); + PP_ASSERT_WITH_CODE((smc_result == 0), + "Failed to disable PkgPwrTracking in SMC.", + result = smc_result); + } + data->power_containment_features = 0; + } + + return result; +} + int fiji_power_control_set_level(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *table_info = |