diff options
| author | Rex Zhu <Rex.Zhu@amd.com> | 2017-05-31 19:29:53 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-06-01 16:00:19 -0400 |
| commit | 040cd2d1f5037be4a1cfe4f4e4b3be248707dc0c (patch) | |
| tree | 55a3664fc713ccabea76e510af020a3818a49884 /drivers/gpu/drm/amd/include/atomfirmware.h | |
| parent | c5b053d2a07b3628ed3a9ccf5082d93762618bf2 (diff) | |
drm/amd/powerplay: Align with VBIOS to support AVFS parameters.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/atomfirmware.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/atomfirmware.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index d38687516d60..0021a1c63356 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1206,10 +1206,10 @@ struct atom_asic_profiling_info_v4_1 uint32_t gb_vdroop_table_ckson_a1; uint32_t gb_vdroop_table_ckson_a2; uint32_t avfsgb_fuse_table_cksoff_m1; - uint16_t avfsgb_fuse_table_cksoff_m2; + uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t avfsgb_fuse_table_cksoff_b; uint32_t avfsgb_fuse_table_ckson_m1; - uint16_t avfsgb_fuse_table_ckson_m2; + uint32_t avfsgb_fuse_table_ckson_m2; uint32_t avfsgb_fuse_table_ckson_b; uint16_t max_voltage_0_25mv; uint8_t enable_gb_vdroop_table_cksoff; @@ -1220,16 +1220,16 @@ struct atom_asic_profiling_info_v4_1 uint8_t enable_apply_avfs_cksoff_voltage; uint8_t reserved; uint32_t dispclk2gfxclk_a; - uint16_t dispclk2gfxclk_b; + uint32_t dispclk2gfxclk_b; uint32_t dispclk2gfxclk_c; uint32_t pixclk2gfxclk_a; - uint16_t pixclk2gfxclk_b; + uint32_t pixclk2gfxclk_b; uint32_t pixclk2gfxclk_c; uint32_t dcefclk2gfxclk_a; - uint16_t dcefclk2gfxclk_b; + uint32_t dcefclk2gfxclk_b; uint32_t dcefclk2gfxclk_c; uint32_t phyclk2gfxclk_a; - uint16_t phyclk2gfxclk_b; + uint32_t phyclk2gfxclk_b; uint32_t phyclk2gfxclk_c; }; |