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| author | Joshua Aberback <joshua.aberback@amd.com> | 2019-08-08 13:22:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-23 11:45:55 -0500 |
| commit | 9a7bfcb6acee07ae891ad28d40a1535aab3134a9 (patch) | |
| tree | 9fdb07ece0ca82e9ba1ede67912cf4c3e7a7380e /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |
| parent | 617089d5837a3aa4167a9c4afb34929e0d52805d (diff) | |
drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL
[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.
[How]
- add relevant fields to shift / mask initialization
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
0 files changed, 0 insertions, 0 deletions