diff options
| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2018-02-22 16:50:39 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-14 15:08:43 -0500 |
| commit | 623a7e96cd73a46d15f64b1c5e1f4ea3548271f2 (patch) | |
| tree | 1080cc9ffe9e6e2f3acf2c1111978412c22bda52 /drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |
| parent | 5e3e341cee51a755b81a660806bfcad3fdcfc906 (diff) | |
drm/amd/display: Remove 300Mhz minimum disp clk limit.
300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c2041a63cccd..ca0484894084 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2106,9 +2106,6 @@ enum dc_status dce110_apply_ctx_to_hw( return status; } - /* pplib is notified if disp_num changed */ - dc->hwss.set_bandwidth(dc, context, true); - /* to save power */ apply_min_clocks(dc, context, &clocks_state, false); |