diff options
author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:32:53 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
commit | 4d55b0dd1cdd8535ffd6057f210465575117d807 (patch) | |
tree | fa71c4f5002239f2af3941270bdb519203eba520 /drivers/gpu/drm/amd/display/dc/core/dc_stream.c | |
parent | be547111d2be16e81dc2d9669cf3caa3675fa55d (diff) |
drm/amd/display: Add DCN3 CLK_MGR
Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_stream.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 4f0e7203dba4..3b897372ed27 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -243,6 +243,9 @@ bool dc_stream_set_cursor_attributes( struct dc *dc; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool reset_idle_optimizations = false; +#endif if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -262,6 +265,15 @@ bool dc_stream_set_cursor_attributes( res_ctx = &dc->current_state->res_ctx; stream->cursor_attributes = *attributes; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* disable idle optimizations while updating cursor */ + if (dc->idle_optimizations_allowed) { + dc->hwss.apply_idle_power_optimizations(dc, false); + reset_idle_optimizations = true; + } + +#endif + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -281,6 +293,12 @@ bool dc_stream_set_cursor_attributes( if (pipe_to_program) dc->hwss.cursor_lock(dc, pipe_to_program, false); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* re-enable idle optimizations if necessary */ + if (reset_idle_optimizations) + dc->hwss.apply_idle_power_optimizations(dc, true); + +#endif return true; } @@ -292,6 +310,9 @@ bool dc_stream_set_cursor_position( struct dc *dc; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool reset_idle_optimizations = false; +#endif if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -305,6 +326,16 @@ bool dc_stream_set_cursor_position( dc = stream->ctx->dc; res_ctx = &dc->current_state->res_ctx; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + + /* disable idle optimizations if enabling cursor */ + if (dc->idle_optimizations_allowed && + !stream->cursor_position.enable && position->enable) { + dc->hwss.apply_idle_power_optimizations(dc, false); + reset_idle_optimizations = true; + } + +#endif stream->cursor_position = *position; for (i = 0; i < MAX_PIPES; i++) { @@ -328,6 +359,12 @@ bool dc_stream_set_cursor_position( if (pipe_to_program) dc->hwss.cursor_lock(dc, pipe_to_program, false); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* re-enable idle optimizations if necessary */ + if (reset_idle_optimizations) + dc->hwss.apply_idle_power_optimizations(dc, true); + +#endif return true; } |