diff options
| author | Jiansong Chen <Jiansong.Chen@amd.com> | 2020-06-24 12:47:54 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-15 12:47:09 -0400 |
| commit | c5b6c914d2f3755426b9c68ed6ddd8f917d9be9e (patch) | |
| tree | abb5fd7cfdf956edbf9168fd69d1ddc5342ec28a /drivers/gpu/drm/amd/amdgpu | |
| parent | 290b4ad59220b021187125f2f585da350eb6dded (diff) | |
drm/amdgpu: enable cp_fw_write_wait for navy_flounder
It's the same with sienna_cichlid, cp fw for navy_flounder
can support WAIT_REG_MEM packet.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3799185430df..61e89247faf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3538,6 +3538,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) adev->gfx.cp_fw_write_wait = true; break; case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: adev->gfx.cp_fw_write_wait = true; break; default: |