diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2019-08-09 16:40:45 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-08-23 09:42:22 +0200 |
| commit | 74639d66e1ec069d27eebb97b545916a86d983ea (patch) | |
| tree | baedf83cdbd3ea4a01a312be4ffe956ca2c44917 /drivers/gpio | |
| parent | e599256ab78b99614b361b551145f3f95c9b3041 (diff) | |
gpio: tqmx86: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.
For chained irqchips this is a pretty straight-forward
conversion.
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809144045.26018-1-linus.walleij@linaro.org
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-tqmx86.c | 41 |
1 files changed, 24 insertions, 17 deletions
diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index d5880db7f9d4..07050cdbadb9 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -219,6 +219,7 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct tqmx86_gpio_data *gpio; struct gpio_chip *chip; + struct gpio_irq_chip *girq; void __iomem *io_base; struct resource *res; int ret, irq; @@ -264,12 +265,6 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); - ret = devm_gpiochip_add_data(dev, chip, gpio); - if (ret) { - dev_err(dev, "Could not register GPIO chip\n"); - goto out_pm_dis; - } - if (irq) { struct irq_chip *irq_chip = &gpio->irq_chip; u8 irq_status; @@ -287,23 +282,35 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); - ret = gpiochip_irqchip_add(chip, irq_chip, - 0, handle_simple_irq, - IRQ_TYPE_EDGE_BOTH); - if (ret) { - dev_err(dev, "Could not add irq chip\n"); + girq = &chip->irq; + girq->chip = irq_chip; + girq->parent_handler = tqmx86_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + ret = -ENOMEM; goto out_pm_dis; } + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } - gpiochip_set_chained_irqchip(chip, irq_chip, - irq, tqmx86_gpio_irq_handler); + ret = devm_gpiochip_add_data(dev, chip, gpio); + if (ret) { + dev_err(dev, "Could not register GPIO chip\n"); + goto out_pm_dis; } /* Only GPIOs 4-7 are valid for interrupts. Clear the others */ - clear_bit(0, chip->irq.valid_mask); - clear_bit(1, chip->irq.valid_mask); - clear_bit(2, chip->irq.valid_mask); - clear_bit(3, chip->irq.valid_mask); + if (irq) { + clear_bit(0, girq->valid_mask); + clear_bit(1, girq->valid_mask); + clear_bit(2, girq->valid_mask); + clear_bit(3, girq->valid_mask); + } dev_info(dev, "GPIO functionality initialized with %d pins\n", chip->ngpio); |