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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2016-03-27 17:43:02 +0200
committerLinus Walleij <linus.walleij@linaro.org>2016-03-31 11:59:43 +0200
commit8fccdb580ebec0f5b081d824797911a4c5d91891 (patch)
tree8dcbb3ffe3d247015b1bdd0856267df1eb8b27d2 /drivers/gpio/gpio-it87.c
parent691998fac6f50c9117e279c3fbfa63a23cf7ce2e (diff)
gpio: gpio-it87: Add support for IT8620 and IT8628
These chips seem to have a 9th GPIO block (thus supporting 72 GPIOs) which is configured through SuperIO register 0xd2 (output enable) and 0xd3 (simple I/O). This is also the reason why io_size is larger than on IT8728 / IT8732. Unfortunately I don't have hardware to test this 9th GPIO block. I am also not sure about not configuring the Simple I/O registers as the hardware I have only uses GPIO block 8. Reading back the values of 0xc0-0xc7 (as configured by the BIOS/EFI on my board) shows that all have 0xff set. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-it87.c')
-rw-r--r--drivers/gpio/gpio-it87.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-it87.c b/drivers/gpio/gpio-it87.c
index b219c82414bf..63a962d18cd6 100644
--- a/drivers/gpio/gpio-it87.c
+++ b/drivers/gpio/gpio-it87.c
@@ -34,6 +34,8 @@
/* Chip Id numbers */
#define NO_DEV_ID 0xffff
+#define IT8620_ID 0x8620
+#define IT8628_ID 0x8628
#define IT8728_ID 0x8728
#define IT8732_ID 0x8732
#define IT8761_ID 0x8761
@@ -302,6 +304,14 @@ static int __init it87_gpio_init(void)
it87_gpio->chip = it87_template_chip;
switch (chip_type) {
+ case IT8620_ID:
+ case IT8628_ID:
+ gpio_ba_reg = 0x62;
+ it87_gpio->io_size = 11;
+ it87_gpio->output_base = 0xc8;
+ it87_gpio->simple_size = 0;
+ it87_gpio->chip.ngpio = 64;
+ break;
case IT8728_ID:
case IT8732_ID:
gpio_ba_reg = 0x62;