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authorGolan Ben Ami <golan.ben.ami@intel.com>2018-02-11 10:48:32 +0200
committerLuca Coelho <luciano.coelho@intel.com>2018-07-26 13:16:14 +0300
commit1b493e30a19540438a9944683aa9310b8077bc80 (patch)
tree6863a7e0168856d116260824b2c383f4904cfe0d /drivers/edac
parent5f01df3f58ab25cffb6b2577339fde1dfe696bf2 (diff)
iwlwifi: pcie: allocate and free rx cr's and tr's tails
The hw now refers to two new blocks: * rx tr tail - The Tail index on the free buffers queue TR, which is update by the device after reading the free buffer from the tr. * rx cr tail - Updated by the driver when completing processing a new completion descriptor in the cr. Add these two new struct to the rxq, allocate and free them when needed. In addition, the register for rx write pointer had been changed to HBUS_TARG_WRPTR. The way to differentiate tx from rx is the queue number. TX range is 0-511, and RX's is 512-527. Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'drivers/edac')
0 files changed, 0 insertions, 0 deletions