diff options
| author | Qiuxu Zhuo <qiuxu.zhuo@intel.com> | 2021-06-11 10:01:19 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2021-06-17 18:19:30 -0700 |
| commit | 4bd4d32e9a38d7ffb091b4109ab63c8f601e5678 (patch) | |
| tree | 59ed1c06888923f84a61e087759d3aba3dbd0db8 /drivers/edac/skx_common.h | |
| parent | 2f4348e5a86198704368a699a7c4cdeb21d569f5 (diff) | |
EDAC/i10nm: Add detection of memory levels for ICX/SPR servers
Current i10nm_edac driver is only for system configured in 1-level
memory. If the system is configured in 2-level memory, the driver
doesn't report the 1st level memory DIMM for the error address, even
if the error occurs in the 1st level memory.
Both Ice Lake servers and Sapphire Rapids servers can be configured
in 2-level memory. Add detection of memory levels to i10nm_edac for
the two kinds of servers so that the driver can report the 2nd level
memory DIMM or the 1st level memory DIMM according to error source.
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210611170123.1057025-3-tony.luck@intel.com
Diffstat (limited to 'drivers/edac/skx_common.h')
| -rw-r--r-- | drivers/edac/skx_common.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index 8b5a49058ce4..34e89f7ddf93 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -133,6 +133,9 @@ struct res_config { /* Per DDR channel memory-mapped I/O size */ int ddr_chan_mmio_sz; bool support_ddr5; + /* SAD device number and function number */ + unsigned int sad_all_devfn; + int sad_all_offset; }; typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, |