diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-07 14:53:42 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-07 14:53:42 -0800 |
| commit | 442d1ba237c81304ccfa33887094e843183645f7 (patch) | |
| tree | 55d516e121f3bc558e808d05ae6407f845456db3 /drivers/edac/amd64_edac_inj.c | |
| parent | fb5131e1880ea1ba3ba7197cd5cc66c9c288f715 (diff) | |
| parent | a135cef79a2927ecff800492a26cd314e9cba996 (diff) | |
Merge branch 'edac-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'edac-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
amd64_edac: Disable DRAM ECC injection on K8
EDAC: Fixup scrubrate manipulation
amd64_edac: Remove two-stage initialization
amd64_edac: Check ECC capabilities initially
amd64_edac: Carve out ECC-related hw settings
amd64_edac: Remove PCI ECS enabling functions
amd64_edac: Remove explicit Kconfig PCI dependency
amd64_edac: Allocate driver instances dynamically
amd64_edac: Rework printk macros
amd64_edac: Rename CPU PCI devices
amd64_edac: Concentrate per-family init even more
amd64_edac: Cleanup the CPU PCI device reservation
amd64_edac: Simplify CPU family detection
amd64_edac: Add per-family init function
amd64_edac: Use cached extended CPU model
amd64_edac: Remove F11h support
Diffstat (limited to 'drivers/edac/amd64_edac_inj.c')
| -rw-r--r-- | drivers/edac/amd64_edac_inj.c | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c index 29f1f7a612d9..688478de1cbd 100644 --- a/drivers/edac/amd64_edac_inj.c +++ b/drivers/edac/amd64_edac_inj.c @@ -23,9 +23,7 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci, if (ret != -EINVAL) { if (value > 3) { - amd64_printk(KERN_WARNING, - "%s: invalid section 0x%lx\n", - __func__, value); + amd64_warn("%s: invalid section 0x%lx\n", __func__, value); return -EINVAL; } @@ -58,9 +56,7 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci, if (ret != -EINVAL) { if (value > 8) { - amd64_printk(KERN_WARNING, - "%s: invalid word 0x%lx\n", - __func__, value); + amd64_warn("%s: invalid word 0x%lx\n", __func__, value); return -EINVAL; } @@ -92,9 +88,8 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci, if (ret != -EINVAL) { if (value & 0xFFFF0000) { - amd64_printk(KERN_WARNING, - "%s: invalid EccVector: 0x%lx\n", - __func__, value); + amd64_warn("%s: invalid EccVector: 0x%lx\n", + __func__, value); return -EINVAL; } @@ -122,15 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci, /* Form value to choose 16-byte section of cacheline */ section = F10_NB_ARRAY_DRAM_ECC | SET_NB_ARRAY_ADDRESS(pvt->injection.section); - pci_write_config_dword(pvt->misc_f3_ctl, - F10_NB_ARRAY_ADDR, section); + pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section); word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word, pvt->injection.bit_map); /* Issue 'word' and 'bit' along with the READ request */ - pci_write_config_dword(pvt->misc_f3_ctl, - F10_NB_ARRAY_DATA, word_bits); + pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits); debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); @@ -157,15 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci, /* Form value to choose 16-byte section of cacheline */ section = F10_NB_ARRAY_DRAM_ECC | SET_NB_ARRAY_ADDRESS(pvt->injection.section); - pci_write_config_dword(pvt->misc_f3_ctl, - F10_NB_ARRAY_ADDR, section); + pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section); word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word, pvt->injection.bit_map); /* Issue 'word' and 'bit' along with the READ request */ - pci_write_config_dword(pvt->misc_f3_ctl, - F10_NB_ARRAY_DATA, word_bits); + pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits); debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); |