diff options
| author | Ben Widawsky <ben.widawsky@intel.com> | 2021-06-10 22:11:13 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-06-12 10:30:41 -0700 |
| commit | ba268647368844ed290e2f7b4da7a28cd12ee049 (patch) | |
| tree | 2a0c54fd82a3a5d0211e58ca0a9d3b831677fa43 /drivers/cxl | |
| parent | 6423035fd26c1ecb72f90ecab909e9afa36942b8 (diff) | |
cxl/component_regs: Fix offset
The CXL.cache and CXL.mem registers begin after the CXL.io registers
which occupy the first 0x1000 bytes. The current code wasn't setting
this up properly for future users of the component registers. It was
correct for the probing code however.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities")
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20210611051113.224328-1-ben.widawsky@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index b134b29923ca..c613dc795498 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -599,7 +599,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, length = 0x20 * decoder_cnt + 0x10; map->hdm_decoder.valid = true; - map->hdm_decoder.offset = offset; + map->hdm_decoder.offset = CXL_CM_OFFSET + offset; map->hdm_decoder.size = length; break; default: |