diff options
| author | Phani Kiran Hemadri <phemadri@marvell.com> | 2019-08-08 12:17:37 +0000 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2019-08-15 21:52:13 +1000 |
| commit | b31c17c852736846c917bbd7f1263ea7258fbdce (patch) | |
| tree | 2ac42c5dd6ebd20dfc4c73262a722293fb27e468 /drivers/crypto/cavium/nitrox/nitrox_dev.h | |
| parent | 43b970fa82131ab4f42789a06bfd68dbc6f2a829 (diff) | |
crypto: cavium/nitrox - Allocate asymmetric crypto command queues
This patch adds support to allocate CNN55XX device AQMQ command queues
required for submitting asymmetric crypto requests.
Signed-off-by: Phani Kiran Hemadri <phemadri@marvell.com>
Reviewed-by: Srikanth Jampala <jsrikanth@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/cavium/nitrox/nitrox_dev.h')
| -rw-r--r-- | drivers/crypto/cavium/nitrox/nitrox_dev.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/crypto/cavium/nitrox/nitrox_dev.h b/drivers/crypto/cavium/nitrox/nitrox_dev.h index 5ee98eca728c..2217a2736c8e 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_dev.h +++ b/drivers/crypto/cavium/nitrox/nitrox_dev.h @@ -10,6 +10,8 @@ #define VERSION_LEN 32 /* Maximum queues in PF mode */ #define MAX_PF_QUEUES 64 +/* Maximum device queues */ +#define MAX_DEV_QUEUES (MAX_PF_QUEUES) /* Maximum UCD Blocks */ #define CNN55XX_MAX_UCD_BLOCKS 8 @@ -208,6 +210,7 @@ enum vf_mode { * @mode: Device mode PF/VF * @ctx_pool: DMA pool for crypto context * @pkt_inq: Packet input rings + * @aqmq: AQM command queues * @qvec: MSI-X queue vectors information * @iov: SR-IOV informatin * @num_vecs: number of MSI-X vectors @@ -234,6 +237,7 @@ struct nitrox_device { struct dma_pool *ctx_pool; struct nitrox_cmdq *pkt_inq; + struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp; struct nitrox_q_vector *qvec; struct nitrox_iov iov; |