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authorXiang Chen <chenxiang66@hisilicon.com>2019-04-11 20:46:37 +0800
committerMartin K. Petersen <martin.petersen@oracle.com>2019-04-12 21:30:12 -0400
commit447f78c0e183892bcdd5664472cfcb8846b9081e (patch)
tree3e14e5daec8eec63ec178f1ae19e92df076f87b5 /drivers/clocksource/timer-rda.c
parenta97fa586800ea1779cfd83f7c06f11e2e6bb44f5 (diff)
scsi: hisi_sas: Remedy inconsistent PHY down state in software
Currently there are two scenarioes which may cause PHY state of hardware (which is 0) is inconsistent with the state held in software: - Unplug SAS wire before get_phys_state when SAS controller reset, then the interrupts of phy down are ignored, phy state is 0 before reset, and it also gets 0 after reset, so phy down doesn't occur even if unplugged SAS wire; - For v3 hw later version, it will close bus when 2 bit ECC error occurs. So if unplug SAS wire at that time, interrupts of phy down also not occur. So at last it will cause host reset. It also get phy state 0 before and after reset, the same issue occurs. To solve it, use hisi_sas_phy_down() directly in rescan topology function. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/clocksource/timer-rda.c')
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