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authorNicolai Hähnle <nicolai.haehnle@amd.com>2018-06-29 13:23:25 +0200
committerAlex Deucher <alexander.deucher@amd.com>2018-07-04 02:40:18 -0500
commitc660f40b711980b42d8beac4b395a10645b20d5d (patch)
tree75cef41fd299770b8249a77be935dcc62a14aeeb /drivers/clocksource/timer-prima2.c
parentc3d0280be8d5c6de9e3848e280493f561799bb67 (diff)
drm/amdgpu: fix user fence write race condition
The buffer object backing the user fence is reserved using the non-user fence, i.e., as soon as the non-user fence is signaled, the user fence buffer object can be moved or even destroyed. Therefore, emit the user fence first. Both fences have the same cache invalidation behavior, so this should have no user-visible effect. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/clocksource/timer-prima2.c')
0 files changed, 0 insertions, 0 deletions