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authorXing Zheng <zhengxing@rock-chips.com>2016-04-20 19:12:10 +0800
committerHeiko Stuebner <heiko@sntech.de>2016-04-25 21:52:32 +0200
commitf3d40914d3d52e2f155c4e65bc2ab5f5d1efb0ab (patch)
treece2d59815f11e0a7c214311eba057ebe27eb699c /drivers/clk
parentb8199ff31f86ee94fa1166997259b03022ecb4de (diff)
clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
The gate bits of the i2c4 and i2c8 are incorrect due to the manual error, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index e8f040be3fea..40b738460d47 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1401,11 +1401,11 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
- RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
+ RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
- RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
+ RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),