diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2014-09-29 20:45:42 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2014-09-30 13:17:47 -0400 |
| commit | 5fb9b1b949ce9b829e7e8f799cc85e91527213bd (patch) | |
| tree | 0ffee65c07f465c1536a7bc1ee9c55240b4eb4d4 /drivers/clk | |
| parent | b874ec8d57ba61cb56c97a7b7810828da8ec8e95 (diff) | |
ath9k_hw: fix PLL clock initialization for newer SoC
On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
register changed. This currently breaks at least 5/10 MHz operation.
AR933x uses the old layout.
It might also have been causing other stability issues because of the
different location of the PLL_BYPASS bit which needs to be set during
PLL clock initialization.
This patch also removes more instances of hardcoded register values in
favor of properly computed ones with the PLL_BYPASS bit added.
Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/clk')
0 files changed, 0 insertions, 0 deletions