diff options
| author | Tang Yuantian <Yuantian.Tang@nxp.com> | 2016-11-24 10:36:55 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-12-08 16:29:30 -0800 |
| commit | 447093584fa38fe9cc4862c946007a07b0e6cbd0 (patch) | |
| tree | e01d92545a040fbe50f3f50161530e366776c7f7 /drivers/clk | |
| parent | f8d17344a60921c2387759fc0a85aa64299d1ec6 (diff) | |
clk: qoriq: added ls1012a clock configuration
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[sboyd@codeaurora.org: Sorted list]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-qoriq.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 7dd4351efdd6..d0bf8b1c67de 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -291,6 +291,14 @@ static const struct clockgen_muxinfo ls1046a_hwa2 = { }, }; +static const struct clockgen_muxinfo ls1012a_cmux = { + { + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, + {}, + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + } +}; + static const struct clockgen_muxinfo t1023_hwa1 = { { {}, @@ -529,6 +537,16 @@ static const struct clockgen_chipinfo chipinfo[] = { .flags = CG_PLL_8BIT, }, { + .compat = "fsl,ls1012a-clockgen", + .cmux_groups = { + &ls1012a_cmux + }, + .cmux_to_group = { + 0, -1 + }, + .pll_mask = 0x03, + }, + { .compat = "fsl,ls2080a-clockgen", .cmux_groups = { &clockgen2_cmux_cga12, &clockgen2_cmux_cgb @@ -1313,6 +1331,7 @@ err: CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); +CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); |