diff options
| author | Tony Lindgren <tony@atomide.com> | 2015-03-22 15:35:24 -0700 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2015-03-24 20:26:05 +0200 |
| commit | 33ca29c99e8680b4c921c6eafb9fc1603c5b9779 (patch) | |
| tree | 7bcae4571d8ff8a3f6859b5dcda71ff6907e5afc /drivers/clk | |
| parent | 712f7d64f079872d2895743f4b718bc0fdff725c (diff) | |
clk: ti: Fix FAPLL recalc_rate for rounding errors
We need to round the calculated value to have it match the requested rate.
While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we
will need it in later patches for set_rate.
And let's remove two unused includes.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ti/fapll.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index 6ef89639a9f6..97138c106a67 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -11,12 +11,10 @@ #include <linux/clk-provider.h> #include <linux/delay.h> -#include <linux/slab.h> #include <linux/err.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/clk/ti.h> -#include <asm/div64.h> /* FAPLL Control Register PLL_CTRL */ #define FAPLL_MAIN_LOCK BIT(7) @@ -49,6 +47,8 @@ /* Synthesizer frequency register */ #define SYNTH_LDFREQ BIT(31) +#define SYNTH_MAX_DIV_M 0xff + struct fapll_data { struct clk_hw hw; void __iomem *base; @@ -218,11 +218,10 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, rate *= 8; } - /* Synth ost-divider M */ - synth_div_m = readl_relaxed(synth->div) & 0xff; - do_div(rate, synth_div_m); + /* Synth post-divider M */ + synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; - return rate; + return DIV_ROUND_UP_ULL(rate, synth_div_m); } static struct clk_ops ti_fapll_synt_ops = { |