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authorYang Yingliang <yangyingliang@huawei.com>2021-06-01 19:41:54 +0800
committerStephen Boyd <sboyd@kernel.org>2021-06-01 23:39:42 -0700
commit06abc7537686ad013825bef6aa0f03fd484ca5ad (patch)
treebec3eb2764d1eabd285cc5a7f099380b690d5123 /drivers/clk
parentc37f1cdd1fc9b128f254c9fb3ec81d0df3cc6117 (diff)
clk: analogbits: fix doc warning in wrpll-cln28hpc.c
Fix the following make W=1 warning: drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210601114154.3163327-1-yangyingliang@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/analogbits/wrpll-cln28hpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 776ead319ae9..3b1947575dcc 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -198,7 +198,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
}
/**
- * wrpll_configure() - compute PLL configuration for a target rate
+ * wrpll_configure_for_rate() - compute PLL configuration for a target rate
* @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)