diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2014-11-13 15:19:21 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-16 00:02:24 +0100 |
| commit | 0132234160ae46d8bd4677e37adb0b4366e05b1e (patch) | |
| tree | bf44e88f39dfbda88915e3bf4a2530c8d009fb33 /drivers/clk | |
| parent | 9aa75e6e09620dbff3ae65ff3f03d2da3129b080 (diff) | |
clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b4a74c2d79e0..f27cdae61fd5 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0, RK3288_CLKSEL_CON(13), 11, 2, MFLAGS, - RK3288_CLKGATE_CON(5), 15, GFLAGS), + RK3288_CLKGATE_CON(5), 14, GFLAGS), COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, RK3288_CLKGATE_CON(3), 6, GFLAGS), |