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authorTero Kristo <t-kristo@ti.com>2014-10-03 16:57:14 +0300
committerPaul Walmsley <paul@pwsan.com>2014-11-13 09:26:45 -0700
commit2e1a7b014f9c3d61fbf12b429f0479242264dbec (patch)
treececb7c3739740f991c03eda4f0fbfd075458cd82 /drivers/clk/ti/clk-43xx.c
parente3ab6013ab06d3a861ed00c1f8d32aa4e6b66ddd (diff)
ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
Currently, DPLLs are hiding the gory details of switching parent within set_rate, which confuses the common clock code and is wrong. Fixed by applying the new determine_rate() and set_rate_and_parent() functionality to any clock-ops previously using the broken approach. This patch also removes the broken legacy code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'drivers/clk/ti/clk-43xx.c')
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