diff options
author | Mark Zhang <markz@nvidia.com> | 2013-08-07 19:25:08 +0800 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-25 16:11:44 +0200 |
commit | fc20eeff6c03fcdbb2b5ac21472778b573850e77 (patch) | |
tree | 152cc4190bdfab23cbca6fae2547419f082a3da8 /drivers/clk/tegra | |
parent | d17cb95fa0b8676a38c0d07e2da26885d4ff8187 (diff) |
clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2
pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 6d6491c7b479..76611289b8e6 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2180,6 +2180,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, + {TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, + {TEGRA114_CLK_GR_3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, + /* This MUST be the last entry. */ {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, }; |