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authorStephen Warren <swarren@nvidia.com>2013-04-04 17:13:54 -0600
committerStephen Warren <swarren@nvidia.com>2013-04-04 17:17:14 -0600
commit964ea47572b89589b61b553e44bbe9907d4f12a6 (patch)
tree242a21cd2e84b72b1f73781528f7696daec6b798 /drivers/clk/tegra
parentc604283f52855a4568c18cfd4011bdcfeccf2c52 (diff)
clk: tegra: fix enum tegra114_clk to match binding
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 0db81dd05fce..d78e16ee161c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -760,7 +760,7 @@ enum tegra114_clk {
pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
- blink, xusb_host_src, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
+ blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
/* Mux clocks */