diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2017-10-04 02:02:40 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:05 +0100 |
| commit | 5a6b184a36b8f5ff01ce93c9251996e4f96310d7 (patch) | |
| tree | a946c7f05398ffa0a3fc65e737d1cc11bdf70b7f /drivers/clk/tegra | |
| parent | 3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0 (diff) | |
clk: tegra: Use common definition of APBDMA clock gate
The APBDMA clock is defined in the common clock gates table that is used
by Tegra30+. Tegra20 can use it too, let's remove the custom definition
and use the common one.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 02b7ab292e97..57a1387ea992 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -523,6 +523,7 @@ static struct tegra_devclk devclks[] __initdata = { static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, + [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true }, [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, @@ -807,11 +808,6 @@ static void __init tegra20_periph_clk_init(void) clk_base, 0, 3, periph_clk_enb_refcnt); clks[TEGRA20_CLK_AC97] = clk; - /* apbdma */ - clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, - 0, 34, periph_clk_enb_refcnt); - clks[TEGRA20_CLK_APBDMA] = clk; - /* emc */ clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), |