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| author | Dmitry Osipenko <digetx@gmail.com> | 2017-10-04 02:02:39 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:04 +0100 |
| commit | 3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0 (patch) | |
| tree | e2a7e4414151d8d37502ab06abbc5d28cabf482f /drivers/clk/tegra/clk-tegra20.c | |
| parent | 899f8095e66c562888ff617686e46019b758611b (diff) | |
clk: tegra: Correct parent of the APBDMA clock
APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
0 files changed, 0 insertions, 0 deletions