diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-01-13 23:24:07 -0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-03-12 11:33:27 +0100 |
| commit | 9a85eb4d62425555ccdc774d906e6bbca5ffccc0 (patch) | |
| tree | 5603e751dc49347f7c79c9cb774fc03ba6c33cfd /drivers/clk/tegra/clk-tegra124.c | |
| parent | 5e7322bbf03694b2bb75de63ae48cff57013d461 (diff) | |
clk: tegra: Add support for OSC_DIV fixed clocks
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
from the OSC pads.
This patch adds support for these clocks.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra124.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index b3110d5b5a6c..32f3dd1ccbad 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, + [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true }, + [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, @@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, + { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 }, + { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, |