diff options
| author | Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:06:48 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-06 14:28:41 +0100 |
| commit | b3cf8d0695056a370276c416979277635c3e4299 (patch) | |
| tree | 270ce13bc347fe5df0ca6d8d39f01e38b6f88213 /drivers/clk/tegra/clk-dfll.h | |
| parent | b0dcfb78dc6aec8698ab5900dfdf6aeae0830815 (diff) | |
clk: tegra: dfll: CVB calculation alignment with the regulator
The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.
When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.
Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-dfll.h')
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 83352c8078f2..85d0d95223f3 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -1,6 +1,6 @@ /* * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver - * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid <afrid@nvidia.com> * Paul Walmsley <pwalmsley@nvidia.com> @@ -22,11 +22,14 @@ #include <linux/reset.h> #include <linux/types.h> +#include "cvb.h" + /** * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @dev: struct device * that holds the OPP table for the DFLL * @max_freq: maximum frequency supported on this SoC * @cvb: CPU frequency table for this SoC + * @alignment: parameters of the regulator step and offset * @init_clock_trimmers: callback to initialize clock trimmers * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage @@ -35,6 +38,7 @@ struct tegra_dfll_soc_data { struct device *dev; unsigned long max_freq; const struct cvb_table *cvb; + struct rail_alignment alignment; void (*init_clock_trimmers)(void); void (*set_clock_trimmers_high)(void); |