diff options
| author | Ryder Lee <ryder.lee@mediatek.com> | 2018-04-17 20:30:27 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-15 15:17:49 -0700 |
| commit | bf61099a21f5a4da3b0551a88d7b3551fa4fff08 (patch) | |
| tree | 7b38a09f9ea99c75d8c76fb1cb1008dbe599a791 /drivers/clk/st | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
The hdmitx_dig_cts clock signal is not a child of clk26m,
and the actual output of the PLL block is derived from
the tvdpll via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/st')
0 files changed, 0 insertions, 0 deletions