diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-06-10 21:52:01 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-27 16:39:59 -0700 |
| commit | dfd1427c3769ba51297777dbb296f1802d72dbf6 (patch) | |
| tree | f525981e9a14e1994ed19e89cee906a460870f4e /drivers/clk/socfpga | |
| parent | c2c9c5661a48bf2e67dcb4e989003144304acd6a (diff) | |
clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.
The previous code never handled the parent mux if there was a
bypass_reg.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga')
| -rw-r--r-- | drivers/clk/socfpga/clk-periph-s10.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index e5a5fef76df7..cbabde2b476b 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -64,16 +64,21 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk) { struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); u32 clk_src, mask; - u8 parent; + u8 parent = 0; + /* handle the bypass first */ if (socfpgaclk->bypass_reg) { mask = (0x1 << socfpgaclk->bypass_shift); parent = ((readl(socfpgaclk->bypass_reg) & mask) >> socfpgaclk->bypass_shift); - } else { + if (parent) + return parent; + } + + if (socfpgaclk->hw.reg) { clk_src = readl(socfpgaclk->hw.reg); parent = (clk_src >> CLK_MGR_FREE_SHIFT) & - CLK_MGR_FREE_MASK; + CLK_MGR_FREE_MASK; } return parent; } |