diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-05-19 22:22:42 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-05-21 15:16:04 -0700 |
| commit | 5343325ff3dd299f459fa9dacbd95dca5c9bf215 (patch) | |
| tree | d24df3d0835c546b13ec9bca3ba2b0551aeac33a /drivers/clk/socfpga/clk.h | |
| parent | 5611a5ba8e5435740df99235b262b553f687b13b (diff) | |
clk: socfpga: add a clock driver for the Arria 10 platform
The clocks on the Arria 10 platform is a bit different than the
Cyclone/Arria 5 platform that it should just have it's own
driver.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/socfpga/clk.h')
| -rw-r--r-- | drivers/clk/socfpga/clk.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index b09a5d50547e..603973ab7e29 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -34,10 +34,14 @@ ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) extern void __iomem *clk_mgr_base_addr; +extern void __iomem *clk_mgr_a10_base_addr; void __init socfpga_pll_init(struct device_node *node); void __init socfpga_periph_init(struct device_node *node); void __init socfpga_gate_init(struct device_node *node); +void socfpga_a10_pll_init(struct device_node *node); +void socfpga_a10_periph_init(struct device_node *node); +void socfpga_a10_gate_init(struct device_node *node); struct socfpga_pll { struct clk_gate hw; @@ -48,6 +52,7 @@ struct socfpga_gate_clk { char *parent_name; u32 fixed_div; void __iomem *div_reg; + struct regmap *sys_mgr_base_addr; u32 width; /* only valid if div_reg != 0 */ u32 shift; /* only valid if div_reg != 0 */ u32 clk_phase[2]; |