diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-24 22:30:18 -0500 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2015-08-24 16:49:03 -0700 |
| commit | 34d5003bfba44a73fe9fbcf75e1d41d130d59bd1 (patch) | |
| tree | 6cb63c13a13c1f257a6c15991cf00dd009864517 /drivers/clk/socfpga/clk.h | |
| parent | 0f350f063eb62212a701a512f74e63ae4714441c (diff) | |
clk: socfpga: Add a second parent option for the dbg_base_clk
The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.
This patch adds the option to get the correct parent for the debug base
clock.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/socfpga/clk.h')
| -rw-r--r-- | drivers/clk/socfpga/clk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index aa2741dbe81a..814c7247bf73 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -22,6 +22,7 @@ /* Clock Manager offsets */ #define CLKMGR_CTRL 0x0 #define CLKMGR_BYPASS 0x4 +#define CLKMGR_DBCTRL 0x10 #define CLKMGR_L4SRC 0x70 #define CLKMGR_PERPLL_SRC 0xAC |