diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2016-11-04 14:58:07 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-11-07 15:16:18 +0100 |
| commit | 0a30284b9fe19780d4587e74578e460469d88706 (patch) | |
| tree | a41ddd1e63cf6a68ee5202de5d61e1dae6445de8 /drivers/clk/socfpga/clk.c | |
| parent | e6e3558626f6dbc16bc13587a1a981dc2446300e (diff) | |
clk: renesas: r8a7795: Fix HDMI parent clock
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/socfpga/clk.c')
0 files changed, 0 insertions, 0 deletions