diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2018-12-17 18:06:14 -0600 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-01-11 15:41:02 -0800 |
| commit | c0a636e4cc2eb39244d23c0417c117be4c96a7fe (patch) | |
| tree | 740172431d775ec750ac2691129d1506d1165a2e /drivers/clk/socfpga/clk-pll-s10.c | |
| parent | 83b4c147967b20b9140e38f7b1a79258a8e9fa6f (diff) | |
clk: socfpga: stratix10: fix rate calculation for pll clocks
The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.
Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-pll-s10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-pll-s10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index 2d5d8b43727e..c4d0b6f6abf2 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, /* Read mdiv and fdiv from the fdbck register */ reg = readl(socfpgaclk->hw.reg + 0x4); mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; - vco_freq = (unsigned long long)parent_rate * (mdiv + 6); + vco_freq = (unsigned long long)vco_freq * (mdiv + 6); return (unsigned long)vco_freq; } |