diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2017-06-08 09:18:39 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-19 17:01:55 -0700 |
| commit | b7f8101d6e75fefd22c39624a30c9ed3d7a72463 (patch) | |
| tree | 69bc892406162ff2d5474256ac99eef0038f26e3 /drivers/clk/socfpga/clk-gate-a10.c | |
| parent | a925810f6ebb89ef94977c4f499264c8fd199dff (diff) | |
clk: socfpga: Fix the smplsel on Arria10 and Stratix10
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-gate-a10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-gate-a10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index c2d572748167..36376c542055 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -86,7 +86,7 @@ static int socfpga_clk_prepare(struct clk_hw *hwclk) } } - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); + hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) regmap_write(socfpgaclk->sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); |