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authorHeiko Stuebner <heiko@sntech.de>2014-02-25 09:50:43 +0900
committerKukjin Kim <kgene.kim@samsung.com>2014-04-15 02:11:36 +0900
commitea5d6a8d3ee606086118d3b4d4b3a49693e92960 (patch)
tree7de9a8a5d1a1b6b771271f9519396395340f267b /drivers/clk/samsung/clk-pll.h
parent42637c59f36198a58069f94676007c62477321b7 (diff)
clk: samsung: add plls used by the early s3c24xx cpus
The manuals do not give them explicit names like in later socs, so more generic names with a s3c2410-prefix were used for them. As it was common to do so in the previous implementation, functionality to change the pll rate is already included. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-pll.h')
-rw-r--r--drivers/clk/samsung/clk-pll.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 5b64bdbb0906..6428bcc6df6f 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -28,6 +28,9 @@ enum samsung_pll_type {
pll_6552,
pll_6552_s3c2416,
pll_6553,
+ pll_s3c2410_mpll,
+ pll_s3c2410_upll,
+ pll_s3c2440_mpll,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \