diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2014-10-09 21:50:29 -0700 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-10-20 12:00:56 +0200 |
| commit | cd9b4609a5621021f6c10ac09e1ddaabc677a814 (patch) | |
| tree | 1902cc8528f7d20bc36cfabad3dbfbfcf7bd02f6 /drivers/clk/rockchip | |
| parent | 61e309f322f264917e5dcbd7ea773df1db53629a (diff) | |
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
This patch add 400MHz and 500MHz to clock rate table for rk3288.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 4670bd8335a1..c3706431ed10 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -86,8 +86,10 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 594000000, 2, 198, 4), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), + RK3066_PLL_RATE( 500000000, 3, 125, 2), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4), |