diff options
author | Finley Xiao <finley.xiao@rock-chips.com> | 2019-09-03 19:59:47 +0800 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2019-09-05 12:43:39 +0200 |
commit | ac68dfd3c4836bb2636fd37f3e075ed218afdb2b (patch) | |
tree | 5208475a94d1a1c0d162cda30aef9fcc3ff88db9 /drivers/clk/rockchip/clk.h | |
parent | efb7740f25d6fff5bf94eb3bfa242b2fe9a6dc36 (diff) |
clk: rockchip: Add clock controller for the rk3308
Add the clock tree definition for the new RK3308 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
-rw-r--r-- | drivers/clk/rockchip/clk.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index b811597a3d38..2271a84124b0 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -121,6 +121,19 @@ struct clk; #define RK3288_EMMC_CON0 0x218 #define RK3288_EMMC_CON1 0x21c +#define RK3308_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3308_GLB_SRST_FST 0xb8 +#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3308_MODE_CON 0xa0 +#define RK3308_SDMMC_CON0 0x480 +#define RK3308_SDMMC_CON1 0x484 +#define RK3308_SDIO_CON0 0x488 +#define RK3308_SDIO_CON1 0x48c +#define RK3308_EMMC_CON0 0x490 +#define RK3308_EMMC_CON1 0x494 + #define RK3328_PLL_CON(x) RK2928_PLL_CON(x) #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) |