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authorChris Brandt <chris.brandt@renesas.com>2018-09-26 08:39:56 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-09-28 09:57:09 +0200
commita53a28dca4124048c90b4a8de457668ede57e67c (patch)
tree528ed82428d6c745f0de4b8a7921067f86133d91 /drivers/clk/renesas
parent4cb1480f5f63178952cd9e457f405fd806260bc0 (diff)
clk: renesas: r7s9210: Add SPI clocks
Add RSPI clocks for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/r7s9210-cpg-mssr.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index d8ff4cb0defc..5135f13ec628 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -95,6 +95,9 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
};
/* The clock dividers in the table vary based on DT and register settings */