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authorFabrizio Castro <fabrizio.castro@bp.renesas.com>2017-10-13 16:22:21 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-10-20 11:00:02 +0200
commit9dc0ddee8d6dcc201b7f9ebc1c0834b0fa306096 (patch)
tree06647c5e33e1ccf985671d8bb1a49cb08ac951cd /drivers/clk/renesas
parentd454cecc637b90996ab15b2e61a6cc51b7e1463c (diff)
clk: renesas: cpg-mssr: Add du1 clock to R8A7745
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/r8a7745-cpg-mssr.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 9e2360a8e14b..2859504cc866 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
DEF_MOD("scif2", 719, R8A7745_CLK_P),
DEF_MOD("scif1", 720, R8A7745_CLK_P),
DEF_MOD("scif0", 721, R8A7745_CLK_P),
+ DEF_MOD("du1", 723, R8A7745_CLK_ZX),
DEF_MOD("du0", 724, R8A7745_CLK_ZX),
DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX),
DEF_MOD("vin1", 810, R8A7745_CLK_ZG),