diff options
| author | Simon Horman <horms+renesas@verge.net.au> | 2019-03-25 17:35:51 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 09:50:48 +0200 |
| commit | 10d9ea5100c89afd677a202036e0e34e129a6c52 (patch) | |
| tree | 8d2e6c4f2701568ac3b13048556dc89989a4be26 /drivers/clk/renesas/rcar-gen3-cpg.h | |
| parent | 20cc05ba04a93f05d6c50789fe35d762a2db4e96 (diff) | |
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.
This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.
As suggested by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 802936625330..9b4bb763f599 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -52,8 +52,8 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ - DEF_BASE(_name, _id, _type, _parent, .div = _div) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) struct rcar_gen3_cpg_pll_config { u8 extal_div; |