diff options
| author | Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> | 2018-07-25 18:10:21 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 10:08:20 +0200 |
| commit | 8d36fdcce21c1713eacf45380696f8cec3d724bf (patch) | |
| tree | aace17ba89b207615d4dae8794da0d390e8a70a6 /drivers/clk/renesas/r8a774a1-cpg-mssr.c | |
| parent | 4aeed945b7024e454bafb4beb68b8c0298832efb (diff) | |
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/r8a774a1-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 44161fd0a09c..bce0e6d6d02c 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -165,8 +165,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2), DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1), DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1), - DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4), + DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2), DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4), DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0), DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0), |