diff options
| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-12-13 19:55:34 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-21 16:03:26 -0800 |
| commit | 32cae024f7186e60cbdeb5b594eb920036f38225 (patch) | |
| tree | 60c329621e6f73ada01bf8288db2232bb0810d01 /drivers/clk/qcom | |
| parent | df964016490b2cf630b1b926a1d5c610833aaa84 (diff) | |
clk: qcom: ipq8074: fix missing GPLL0 divider width
GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq8074.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index ed2d00f55378..99906f6a8264 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -84,6 +84,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ |