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authorRajendra Nayak <rnayak@codeaurora.org>2016-11-18 17:58:26 +0530
committerStephen Boyd <sboyd@codeaurora.org>2016-11-23 16:41:15 -0800
commit904bb4f5c7de2f40ff31d43d3547d40910e46640 (patch)
tree5268fb9049fcf4576592d6e800c83ecd249bc870 /drivers/clk/qcom/gdsc.h
parent5e2035b90e7192b48f9615ddfbcc6fef1149ed8a (diff)
clk: qcom: gdsc: Add support for gdscs with HW control
Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/gdsc.h')
-rw-r--r--drivers/clk/qcom/gdsc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index f011c4957527..39648348e5ec 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -52,6 +52,7 @@ struct gdsc {
const u8 flags;
#define VOTABLE BIT(0)
#define CLAMP_IO BIT(1)
+#define HW_CTRL BIT(2)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;