diff options
| author | Michael Turquette <mturquette@baylibre.com> | 2016-04-28 12:01:42 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2016-06-22 18:02:28 -0700 |
| commit | ec623f2a43ebe482abc925f8785f462c0fe3c08a (patch) | |
| tree | ad3b7e1ea8077e360ab312e35a4a15d2748652f7 /drivers/clk/meson/clkc.h | |
| parent | e92f7cca446ec503251b58ad9a8b5592a2d927de (diff) | |
clk: meson8b: clean up pll clocks
Remove the pll registration function and helpers. Replace unnecessary
configuration struct with static initialization of the desired clock
type.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 52 |
1 files changed, 25 insertions, 27 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index b23b057d86e1..0bb4fb88a1a9 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -34,12 +34,13 @@ struct parm { u8 shift; u8 width; }; -#define PARM(_r, _s, _w) \ - { \ - .reg_off = (_r), \ - .shift = (_s), \ - .width = (_w), \ - } \ + +#define PARM(_r, _s, _w) \ +{ \ + .reg_off = (_r), \ + .shift = (_s), \ + .width = (_w), \ +} \ struct pll_rate_table { unsigned long rate; @@ -55,13 +56,19 @@ struct pll_rate_table { .od = (_od), \ } \ -struct pll_conf { - const struct pll_rate_table *rate_table; - struct parm m; - struct parm n; - struct parm od; +struct meson_clk_pll { + struct clk_hw hw; + void __iomem *base; + struct parm m; + struct parm n; + struct parm od; + const struct pll_rate_table *rate_table; + unsigned int rate_count; + spinlock_t *lock; }; +#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) + struct fixed_fact_conf { unsigned int div; unsigned int mult; @@ -86,7 +93,6 @@ enum clk_type { CLK_FIXED_FACTOR, CLK_COMPOSITE, CLK_CPU, - CLK_PLL, }; struct clk_conf { @@ -100,23 +106,10 @@ struct clk_conf { union { struct fixed_fact_conf fixed_fact; const struct composite_conf *composite; - struct pll_conf *pll; const struct clk_div_table *div_table; } conf; }; -#define PLL(_ro, _ci, _cn, _cp, _f, _c) \ - { \ - .reg_off = (_ro), \ - .clk_type = CLK_PLL, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .clks_parent = (_cp), \ - .num_parents = ARRAY_SIZE(_cp), \ - .flags = (_f), \ - .conf.pll = (_c), \ - } \ - #define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \ { \ .clk_type = CLK_FIXED_FACTOR, \ @@ -155,7 +148,12 @@ void meson_clk_register_clks(const struct clk_conf *clk_confs, unsigned int nr_confs, void __iomem *clk_base); struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf, void __iomem *reg_base, spinlock_t *lock); -struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf, - void __iomem *reg_base, spinlock_t *lock); + +/* shared data */ +extern spinlock_t clk_lock; + +/* clk_ops */ +extern const struct clk_ops meson_clk_pll_ro_ops; +extern const struct clk_ops meson_clk_pll_ops; #endif /* __CLKC_H */ |