diff options
author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:43 +0100 |
---|---|---|
committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:04:03 +0100 |
commit | d610b54f77002bbddca54c10d9488c2faa7ff102 (patch) | |
tree | a991e55607dc05c8f35690122bb66dad30ae55ec /drivers/clk/meson/clk-mpll.c | |
parent | 722825dcd54b2e427c1aee54a7992eb4ab04a49d (diff) |
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.
This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clk-mpll.c')
-rw-r--r-- | drivers/clk/meson/clk-mpll.c | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 66998ff47635..0df1227b65b3 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -170,57 +170,13 @@ static int mpll_set_rate(struct clk_hw *hw, return 0; } -static void mpll_enable_core(struct clk_hw *hw, int enable) -{ - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); - unsigned long flags = 0; - - if (mpll->lock) - spin_lock_irqsave(mpll->lock, flags); - else - __acquire(mpll->lock); - - meson_parm_write(clk->map, &mpll->en, enable ? 1 : 0); - - if (mpll->lock) - spin_unlock_irqrestore(mpll->lock, flags); - else - __release(mpll->lock); -} - - -static int mpll_enable(struct clk_hw *hw) -{ - mpll_enable_core(hw, 1); - - return 0; -} - -static void mpll_disable(struct clk_hw *hw) -{ - mpll_enable_core(hw, 0); -} - -static int mpll_is_enabled(struct clk_hw *hw) -{ - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); - - return meson_parm_read(clk->map, &mpll->en); -} - const struct clk_ops meson_clk_mpll_ro_ops = { .recalc_rate = mpll_recalc_rate, .round_rate = mpll_round_rate, - .is_enabled = mpll_is_enabled, }; const struct clk_ops meson_clk_mpll_ops = { .recalc_rate = mpll_recalc_rate, .round_rate = mpll_round_rate, .set_rate = mpll_set_rate, - .enable = mpll_enable, - .disable = mpll_disable, - .is_enabled = mpll_is_enabled, }; |