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| author | Peng Fan <peng.fan@nxp.com> | 2020-04-28 15:21:00 +0800 |
|---|---|---|
| committer | Viresh Kumar <viresh.kumar@linaro.org> | 2020-04-28 14:26:20 +0530 |
| commit | 7c2553f0db6133ba079597422391661914ce91c7 (patch) | |
| tree | 964c28ced1f1486163bff5489c9c46f527100291 /drivers/clk/mediatek/clk-mt6779-mm.c | |
| parent | a6d1bfa05545b0d34f5b5093248b10a745c050e3 (diff) | |
cpufreq: imx-cpufreq-dt: support i.MX7ULP
i.MX7ULP's ARM core clock design is totally different compared
with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs
get_intermediate and target_intermedate to configure clk MUX ready,
before let OPP configure ARM core clk.
|---FIRC
|------RUN---...---SCS(MUX2) --------|
ARM --(MUX1) |---SPLL_PFD0(CLK_SET_RATE_GATE)
|------HSRUN--...--HSRUN_SCS(MUX3)---|
|---SRIC
FIRC is step clk, SPLL_PFD0 is the normal clk driving ARM core.
MUX2 and MUX3 share same inputs. So if MUX2/MUX3 both sources from
SPLL_PFD0, both MUXes will lose input when configure SPLL_PFD0.
So the target_intermediate will configure MUX2/MUX3 to FIRC, to avoid
ARM core lose clk when configure SPLL_PFD0.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt6779-mm.c')
0 files changed, 0 insertions, 0 deletions