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authorWeiyi Lu <weiyi.lu@mediatek.com>2019-03-05 13:05:45 +0800
committerStephen Boyd <sboyd@kernel.org>2019-04-11 13:29:19 -0700
commitacddfc2c261b3653ab1c1b567a427299bac20d31 (patch)
treebdacafd8bc6ece8d1219198e7eb9d4fec6743a9e /drivers/clk/mediatek/clk-gate.h
parent23fe31dedb7b1836cc23666afc1a9c67ed7de775 (diff)
clk: mediatek: Add MT8183 clock support
Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-gate.h')
-rw-r--r--drivers/clk/mediatek/clk-gate.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 9f766dfe1d57..ab240163f9f8 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate(
const struct clk_ops *ops,
unsigned long flags);
+#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
+ _ops, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _regs, \
+ .shift = _shift, \
+ .ops = _ops, \
+ .flags = _flags, \
+ }
+
+#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
+ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
+
#endif /* __DRV_CLK_GATE_H */