diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2021-06-04 17:09:41 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2021-06-14 12:34:43 +0300 |
| commit | 7487986c9a010410b7e7af13072a5c04ea804eda (patch) | |
| tree | 0ecb061c1854c9b4d55631639d22ee70a53be9ce /drivers/clk/imx | |
| parent | a43f6e8ae429f5ca594ae4463cc31c2a8ad4339c (diff) | |
clk: imx: scu: Only save DC SS clock using non-cached clock rate
Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx')
| -rw-r--r-- | drivers/clk/imx/clk-scu.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 9f7ad3ca1039..37919ffc46a2 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -547,7 +547,14 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) (rsrc_id == IMX_SC_R_A72)) return 0; - clk->rate = clk_hw_get_rate(&clk->hw); + /* DC SS needs to handle bypass clock using non-cached clock rate */ + if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1) + clk->rate = clk_scu_recalc_rate(&clk->hw, 0); + else + clk->rate = clk_hw_get_rate(&clk->hw); clk->is_enabled = clk_hw_is_enabled(&clk->hw); if (clk->rate) |