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author | Chen-Yu Tsai <wens@csie.org> | 2015-03-25 01:22:08 +0800 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-03-25 11:46:41 -0700 |
commit | f1017969661dd33ead5ba7c3f4a0793c6611441a (patch) | |
tree | b4e6aec3ce3765f5c6692abec131768ffa8110bc /drivers/clk/berlin | |
parent | 934fe5f48ae52841f8a5f5e0411147a8ccd171c1 (diff) |
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
The pll6 has a /4 output that is used as an input to the ahb mux clock.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/berlin')
0 files changed, 0 insertions, 0 deletions